Method and system for translating peripheral component interconn

Details Method and system for translating peripheral component interconn Method and system for translating peripheral component interconn

1996-12-13

1999-04-27

Harrell, Robert B.

395306, 395287, G06F 1340

Patent

active

058988882

ABSTRACT:
A method and system for translating peer-to-peer access across multiple Peripheral Component Interconnect (PCI) host bridges within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. A first and at least a second PCI local buses are also connected to the system bus via a first PCI host bridge and a second PCI host bridge, respectively. The two PCI local buses have bus transaction protocols that are different from those of the system bus. At least one PCI device is connected to each of the two PCI local buses, and shares data with the processor and the system memory. In addition, each PCI device shares data with the other PCI device as peer-to-peer devices across multiple PCI host bridges. A sequence of transactions is controlled through the two PCI host bridges to prevent a deadlock condition by not allowing a subsequent peer-to-peer write request destined for one of the two PCI local buses to be blocked from making progress through the two PCI host bridges.

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