Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Patent
1995-11-03
1998-11-03
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
257350, 257351, 257359, 257328, 257355, 257357, 257377, 257538, H01L 902, H01L 2702
Patent
active
058313265
ABSTRACT:
A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions.
REFERENCES:
patent: 4178674 (1979-12-01), Liu et al.
patent: 4180826 (1979-12-01), Shappir
patent: 4214917 (1980-07-01), Clark et al.
patent: 4290185 (1981-09-01), McKenny et al.
patent: 4367580 (1983-01-01), Guterman
patent: 4370798 (1983-02-01), Lien et al.
patent: 4505026 (1985-03-01), Bohr et al.
patent: 4554729 (1985-11-01), Tanimura et al.
patent: 4560419 (1985-12-01), Bourassa et al.
patent: 4561907 (1985-12-01), Raicu
patent: 4619037 (1986-10-01), Taguchi et al.
patent: 4755480 (1988-07-01), Yan et al.
patent: 4796081 (1989-01-01), Cheung et al.
patent: 4805147 (1989-02-01), Yamanaka et al.
patent: 4872042 (1989-10-01), Baba et al.
patent: 4877483 (1989-10-01), Bergemont et al.
patent: 4905068 (1990-02-01), Satoh et al.
patent: 4950620 (1990-08-01), Harrington III
patent: 4966864 (1990-10-01), Pfiester
patent: 5151376 (1992-09-01), Spinner III
patent: 5187114 (1993-02-01), Chan et al.
patent: 5198382 (1993-03-01), Campbell et al.
patent: 5365099 (1994-11-01), Phipps et al.
patent: 5397914 (1995-03-01), Suda et al.
patent: 5502338 (1996-03-01), Suda et al.
IEEE Trans. Electron. Dev., vol. 32, No. 9, Sept. 1985, "Ion-Implanted Thin Polycrystalline High-Value Resistors for High-Density Poly-Load Static Ram Applications," Ohzone et al.
IEEE Trans. Electron. Dev., vol. 4, No. 2, Feb. 1993, "Experimental Characterization of the Diode-Type Polysilicon Loads for CMOS SRAM," Kalnitsky et al., pp. 358-363.
IEEE Trans. Electron. Dev., vol. 30, No. 1, Jan. 1993, "Gigaohm-Range Polycrystalline Silicon Resistors for Microelectronic Applications," Mohan et al., pp. 45-51.
IEEE J. of Solid State Cir., vol. 18, No. 5, Oct. 1983, "A 4.5 ns Access Time 1K x 4 Bit ECL RAM," Hwang et al., pp. 515-520.
IEEE J. of Solid State Cir., vol. 24, No. 2, Apr. 1989, "A Bipolar ECL Static RAM Using Polysilicon Diode Loaded Memory Cell," Hwang et al., pp. 504-511.
IEEE GaAs IC Syposium, 1984, Hyashi et al., "ECL-Compatible GaAs SRAM Circuit Technology for High Performance Computer Applications," pp. 111-114.
IEEE J. of Solid State Cir., vol. 21, No. 5, Oct. 1986, "A 1.0 ns 5-Kbit ECI RAM," Chuang et al., pp. 670-674.
Physics of Semiconductors, S.M. Sze, 1981, pp. 304-305.
Solid State Elect., vol. 30, No. 3, pp.339-343, 1987, "Characterization of Aluminum/LPCVD Polysilicon Schottky Barrier Diodes," Chen et al.
Solid State Elect., vol. 28, No. 12, pp. 1255-1261, 1985, "Field Enhanced Emission and Capture in Polysilicon pn Junctions," Greve et al.
Solid State Electronics, vol. 15, pp. 1103-1106, 1972, "P-N Junctions in Polycrystalline Silicon Films," Manoliu et al.
1989 Symposium on VLSI Technology, Digest of Technical Papers, pp. 61-62, May 22-25, "A New Process Technology for a 4Mbit SRAM With Polysilicon Load Resistor Cell," Yazuriha et al.
Silicon Processing for the VLSI Era, vol. 2--Process Integration, pp. 84-85, 176-177, x-xv, 1986, Wolf.
Hardee, et al. A Fault-Tolerant 30 ns/375 mW 16K x 1 NMOS Static RAM. IEEE Journal of Solid State Circuits, v 16, 435 (1981).
Kang, et al. A 30 ns 6K x 1 Fully Static RAM. IEEE Journal of Solid State Circuits, v 16, 444 (1981).
Yu, et al. HMOS-CMOS --A Low-Power High-Performance Technology. IEEE Journal of Solid State Circuits, v 16, 454 (1981).
Isobe, et al. An 18 ns CMOS/SOS 4K Static RAM. IEEE Jounal of Solid State Circuits, v 16, 460 (1981).
Minato, et al. A Hi-CMOSII 8K x 8 Bit Static RAM. IEEE Journal of Solid State Circuits, v 17, 793 (1982).
Ochii, et al. An Ultralow Power 8K.times.8-Bit Full CMOS With a Six-Transistor Cell. IEEE Journal of Solid State Circuits, v 17, 798 (1982).
Ohzone, et al. An 8K.times.8 bit Static MOS RAM Fabricated by n-MOS
-Well CMOS Technology. IEE Journal of Solid State Circuits, v 15, 854 (1980).
Minato, et al. A High-Speed Hi-CMOSII 4K Static RAM. IEEE Journal of Solid State Circuits, v 16, 449 (1981).
Anami, et al. A 35 ns 16K NMOS Static RAM. IEEE Journal of Solid State Circuits, v 17, 815 (1982).
Uchida, et al. A Low Power Resistive Load 64 kbit CMOS RAM. IEEE Journal of Solid State Circuits, v 17, 804 (1982).
Wada, et al. A 16 DIP, 64 kbit, Static MOS-RAM. IEEE Journal of Solid State Circuits, v 16, 488 (1981).
Ishikawa, et al. An Mo Gate 4K Static MOS RAM. IEEE Journal of Solid State Circuits, v 15, 651 (1980).
Minato, et al. 2K.times.8 Bit Hi-CMOS Static RAM's. IEEE Journal of Solid State Circuits, v 15, 656 (1980).
Wada, et al. A 15-ns 1024-Bit Fully Static MOS RAM. IEEE Journal Of Solid State Curcuits, 635 (1978).
Kang et al. A 30 ns 16.times.1 Fully Static RAM. IEEE Journal of Solid State Circuits, 18, (1981).
Masuhara, et al. 2K.times.8b HCMOS Static RAMS. IEEE Journal of Solid State Circuits, 224 (1980).
Furnweger, Charles. Dynamic Interfacing, Spare Cells Raise 16-K Static Ram's Speed and Yield. Electronics, 121 (1982).
Sud, et al. 16-K Static RAM Takes New Route to High Speed. Electronics, 117 (1980).
Dutoit, et al. Lateral Polysilicon p-n Diodes. J. Electrochem. Soc., v. 125, 1648 (1978).
Dutoit. Influence of Impurities on Lateral Polysilicon pn Diodes. J. Electrochem. Soc. v 130, 967 (1983).
Saito, et al. I-V Characterisctics of Polycrystalline Silicon with n.sup.+ pn.sup.+ Structure. J. Appl. Phys., v 15, 1190 (1985).
Liu, et al. A High-Perfromance MOS Technology for 16K Static RAM. IEDM, 352 (1979).
Iuzuka, et al. Variable Resistance Polysilicon for High Density CMOS RAM. IEDM, 370 (1979).
Morimoto, et al. High Speed 4 kbit Static RAM With Silicone Coated Wiring. Japanese Journal of Applied Physics, v 20, 123 (1981).
Choi, et al. Fabrication of Polysilicon Resistors Compensated With Double Ion-Implantation. Abstract No. 516, 754 (1984).
Rideout, V. Leo. Future Directions in MOSFET Random Access Memories. 4 (1980).
Taubenest, et al. Polycrystalline Silicon Integrated Thin Film Resistors.
Bishop William A.
Chan Tsiu Chiu
Abraham Fetsum
Carlson David V.
Galanthay Theodore E.
Jorgenson Lisa K.
STMicroelectronics Inc.
LandOfFree
Semiconductor device with resistive load element does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with resistive load element, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with resistive load element will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-692534