Floating gate memory with improved dielectric

Static information storage and retrieval – Floating gate – Particular biasing

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257319, G11C 1140

Patent

active

RE0345350

ABSTRACT:
The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide
itride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.

REFERENCES:
patent: 3895360 (1975-07-01), Cricchi et al.
patent: 4115914 (1978-09-01), Harari
patent: 4122544 (1978-10-01), McElroy
patent: 4203158 (1980-05-01), Dov Frohman-Bentchkovsky et al.
patent: 4209849 (1980-06-01), Schrenk
patent: 4270262 (1981-06-01), Hori et al.
patent: 4302766 (1981-11-01), Guterman et al.
patent: 4329706 (1982-05-01), Crowder et al.
patent: 4340953 (1982-07-01), Iwamura et al.
patent: 4399449 (1983-08-01), Herman et al.
patent: 4409723 (1983-10-01), Harari
patent: 4426764 (1984-01-01), Kosa et al.
patent: 4446536 (1984-05-01), Rodgers
patent: 4451904 (1984-05-01), Sugiura et al.
patent: 4455568 (1984-06-01), Shiota
patent: 4456978 (1984-06-01), Morley et al.
patent: 4466172 (1984-08-01), Batra
patent: 4490900 (1985-01-01), Chiu
patent: 4495693 (1985-01-01), Iwahashi et al.
patent: 4532022 (1985-07-01), Takasaki et al.
patent: 4581622 (1986-04-01), Takasaki et al.
patent: 4630086 (1986-12-01), Sato et al.
patent: 4668970 (1987-05-01), Yatsuda et al.
Takashi Ito, et al., "Low-Voltage Alterable EAROM Cells with Nitride-Barrier Avalance-Injection MIS (NAMIS)," Jun., 1979, IEEE Trans. on Electron Devices, vol. ED-26, No. 6, p. 906.
Eiichi Suzuki, et al., "A Low-Voltage Alterable EEPROM with Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) Structures", Feb., 1983, IEEE Transactions on Electron Devices, vol. ED-30, No. 2, p. 122.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Floating gate memory with improved dielectric does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Floating gate memory with improved dielectric, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating gate memory with improved dielectric will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-690931

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.