Method and apparatus for testing a device

Details Method and apparatus for testing a device Method and apparatus for testing a device

1995-12-21

1999-04-27

Beausoliel, Jr., Robert W.

Excavating

371 2234, G01R 3128

Patent

active

058987010

ABSTRACT:
A novel method and apparatus for testing a device is described. The novel method and apparatus uses a reduced number of method steps, instructions, and clock cycles in order to test a device. In one embodiment of the present invention, a method for testing a device is described in which a device is instructed in one instruction to receive address information and a first data packet. The address information and the first data packet are loaded into the device. The first data packet may be selectively passed through a first storage element into a second storage element, and the address information may be loaded into the first storage element. The device is then instructed to program the first data packet into an address location of said device defined by the address information stored in the device. The device is then instructed to read or capture a second data packet from the address location defined by the address information. The second data packet is then output from the device. The second data packet may then be compared with the first data packet to verify the correct initial programming of the first data packet at the address location in the device. Additionally, the device may be instructed to selectively receive a third data packet and then load the third data packet into the device without overwriting the address information already stored in the device. The first data packet and the address information may be serially shifted into the device or loaded in parallel into the device. In like manner, the second data packet may be serially shifted out of the device or outputted in a parallel manner.

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IEEE Standard Test Access Port and Boundary-Scan Architecture, Institute of Electrical and Electronics Engineers, Inc., New York, pp. 1:1-5; 2:1-6; 3:1-9; 4:1:1-5; 2:1-6; 3:1-9; 4:1-3; 5:1-16; 6:1-4; 7:1-28; 8:1-7; 9:1-2; 10:1-45; 11:1-5; 12:1-6; A:1-12, (Oct. 1993).
Cypress Semiconductor Corporation, "7C322D/7C22H Programming Specification (Flash 22V10)", pp. 1-48, Document No. 40-00039.

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