Specialized millicode instructions which reduce cycle time and n

Details Specialized millicode instructions which reduce cycle time and n Specialized millicode instructions which reduce cycle time and n

1997-03-31

1998-05-05

Lall, Parshotam S.

395565, G06F 922, G06F 9305

Patent

active

057489513

ABSTRACT:
A special Program Status Word (PSW) millicode routine, tests the validity of the PSW with three simple millicode instructions. Testing for access exceptions is executed by a special millicode instruction "Load With Access Test", which explicitly detects access exceptions for storage operands while retaining control in the current millicode routine. A Translate and Test (TRT) routine uses a table of 256 bytes to translate a string of bytes. Each string is used as an index into the table, and the selected table byte is fetched. For Translate and Test, the selected bytes are tested, and the first non-zero table byte selected is returned to the program in a general register along with the address of the string byte which selected it; translate and test also sets the condition code, and does not update storage. To provide reasonable performance on Translate and Translate and Test, while maintaining flexibility and simplicity of a millicoded design, a millicode instruction Translate Fetch (TRFET) is provided specifically for use in execution of the Translate and Translate and Test instructions. This Translate Fetch millicode instruction uses an RX format, but modifies the interpretation of the certain fields.

REFERENCES:
Intel "Intel Processor Indentification with the CPUID Instruction" AP-485 pp. 1-18, Oct. 1993.
Digital "VAX11 Architecture Handbook" p. 236, 1979.
"Structured Computer Organization" Andrew S. Tanenbaum pp. 235-236 & 267-269, 1984.
Texas Instruments "Digital Signal Processor Products" pp. 3-7, 1983.
Motorola "Enhanced 32-bit microprocessor user's manual" pp. 3-66, 1989.

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