Semiconductor memory device

Static information storage and retrieval – Addressing

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365189, G11C 800

Patent

active

046352333

ABSTRACT:
A semiconductor memory device has three address decoder circuits that select word lines. Since the word lines are selected by the three address decoder circuits, it is allowed to reduce the number of unit decoder circuits that constitute the address decoder circuits. Therefore, the load for the address buffer circuit can be reduced, and operation can be carried out at high speeds. Further, the decrease in the number of unit decoder circuits results in the decrease in the consumption of electric power.

REFERENCES:
patent: 4316265 (1982-02-01), Tanaka et al.
patent: 4482984 (1984-11-01), Oritani

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