Instruction buffer bypass apparatus

Details Instruction buffer bypass apparatus Instruction buffer bypass apparatus

1983-05-02

1987-01-06

Shaw, Gareth D.

Boots, shoes, and leggings

364900, G06F 930

Patent

active

046351949

ABSTRACT:
A bypass apparatus in a computer system is disclosed. The computer system includes a central storage facility for storing various instructions to be executed, an instruction register for storing an instruction being executed, and an instruction buffer, interconnected between the central storage facility and the instruction register, for temporarily storing the next instructions to be executed following execution of the instruction stored in the instruction register. A bypass path interconnects the central storage facility directly to the instruction register for bypassing the instruction buffer when certain special instructions being held in the instruction register are being executed, such as an EXECUTE instruction. Consequently, the contents of the instruction buffer are not lost or destroyed as a result of execution of the special instruction. The computer system further includes an execute register interconnected between the central storage facility and the instruction register for storing one or more bytes of the instruction being executed when the byte-length of the instruction is greater than the byte-length of the instruction register which stores said instruction.

REFERENCES:
patent: 4040030 (1977-08-01), Cassonnet
patent: 4040031 (1977-08-01), Cassonnet
patent: 4075686 (1978-02-01), Calle et al.
patent: 4156906 (1979-05-01), Ryan
patent: 4217640 (1980-08-01), Porter et al.
patent: 4268907 (1981-05-01), Porter et al.
patent: 4500954 (1985-02-01), Duke et al.

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