Method for forming semiconductor field region dielectrics having

Details Method for forming semiconductor field region dielectrics having Method for forming semiconductor field region dielectrics having

1996-04-17

1998-11-03

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437228, 437235, 1566281, H01L 2131

Patent

active

058307737

ABSTRACT:
An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of field dielectric having an upper surface substantially coplanar with each other and with adjacent silicon mesa upper surfaces. The isolation process is thereby a planarization process used with the shallow trench technique, wherein etch-enhancing ions are forwarded into the fill dielectric at upper elevational regions of that dielectric. When subjected to a subsequent etchant, the dopants cause the higher elevational regions to be removed at a faster rate than the lower elevational regions. Thus, selective placement of dopants and etch removal pre-conditions the fill dielectric upper surface to a more planar surface globally across the entire wafer. After etch removal predominantly at the higher elevational regions, the remaining fill dielectric upper surface is removed to a level commensurate with the upper surface of silicon mesas thereby producing separate field dielectrics interposed between silicon mesas. The field dielectrics, regardless of their lateral area, each have a substantially planar upper surface at or slightly below the adjoining silicon mesas. By producing planar field dielectric upper surfaces, various problems of non-planarity are removed from the thin films which are thereafter formed on the field dielectrics or between the field dielectrics and silicon mesas.

REFERENCES:
patent: 4662064 (1987-05-01), Hsu et al.
patent: 5413953 (1995-05-01), Chien et al.
patent: 5441094 (1995-08-01), Pasch
International Search Report for PCT/US 97/02502, dated Jun. 4, 1997.
Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 1, (1986) pp. 183-185, 321-323.
Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 2 (1990) pp. 200-201. 222-226, 238-239.

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