Shared RAM access arrangement

Details Shared RAM access arrangement Shared RAM access arrangement

1995-03-23

1997-02-04

Harvey, Jack B.

395308, G06F 1300

Patent

active

056008040

ABSTRACT:
Apparatus for providing shared access to a shared RAM in situations where the shared RAM is electrically connected to a relatively slow address/data bus, and shared access is desired from a relatively faster address bus and data bus. An address buffer is connected between the address bus and the address/data bus, the address buffer for selectably buffering address information between those buses under control of an address buffer selection signal. A data buffer is connected between the data bus and the address/data bus, the data buffer for selectably buffering data information between those buses under control of a data buffer selection signal. A gate array is connected to the address/data bus, the gate array controlling access the shared RAM. A logic array is connected to the address bus and is responsive to address information on the address bus which corresponds to addresses of the shared RAM. In response to those addresses, the logic array activates the address buffer selection signal so as to cause the address buffer to buffer address information from the address bus onto the address/data bus, and thereafter by deactivating the address buffer selection signal and activating the data buffer selection signal so as to cause the data buffer to buffer data information from or to the address/data bus.

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Ken Wood, "The Design of a Bus Access Controller Using a PLD", Electronic Engineering, vol. 64, No. 784, Apr., 1992, pp. 47, 48, 51 and 53.

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