Fault resilient/fault tolerant computing

Details Fault resilient/fault tolerant computing Fault resilient/fault tolerant computing

1995-03-16

1997-02-04

Beausoliel, Jr., Robert W.

Excavating

371 471, 364269, 364DIG1, 395551, 395553, G06F 1100, G01R 3128

Patent

active

056007841

ABSTRACT:
In a first aspect, a method of synchronizing at least two computing elements that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements, monitoring the computing elements to detect the production of a selected signal by one of the computing elements, waiting for the other computing elements to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements based on the time updates.
In a second aspect, fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing elements.
Computer systems include one or more controllers and at least two computing elements. System is provided for intercepting I/O operations by the computing elements and transmitting them to the one or more controllers.

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"Low Cost Device For Contention-Free Barrier Synchronization," IBM Technical Disclosure Bulletin, vol. 31, No. 11, Apr. 1989, Armonk, NY, pp. 382-389.

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