On-chip misalignment indication

Details On-chip misalignment indication On-chip misalignment indication

1997-10-03

1999-04-27

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

257528, H01L 2978, H01L 3300

Patent

active

058982280

ABSTRACT:
An on-chip misalignment indicator for measuring misalignment between layers of an integrated circuit die employs a first contact, and a second contact. A current path between the first and second contacts has a resistance that varies as a function of misalignment between successive layers of the integrated circuit die. Similarly, a method for detecting misalignment between layers of an integrated circuit die involves passing and measuring a current between a first contact and a second contact. The amount of the current is indicative of an amount of misalignment between layers of the integrated circuit die.

REFERENCES:
patent: 5701013 (1997-12-01), Hsia et al.
patent: 5753391 (1998-05-01), Stone et al.

Affiliated with

Also associated with

Rating

On-chip misalignment indication does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with On-chip misalignment indication, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-chip misalignment indication will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-687142