Semiconductor memory device that can read out data at high speed

Details Semiconductor memory device that can read out data at high speed Semiconductor memory device that can read out data at high speed

1995-05-05

1997-02-04

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365233, 36523008, G11C 800

Patent

active

056006071

ABSTRACT:
A .phi..sub.C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a .phi..sub.D and PAE generation circuit. The .phi..sub.D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.

REFERENCES:
patent: 5083296 (1992-01-01), Hara
patent: 5210715 (1993-05-01), Houston
patent: 5341341 (1994-08-01), Fukuzo
Toshiba Review, 1993, by S. Sugiura et al., vol. 48, No. 12, pp. 915-918.

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