Method of making porous-si capacitor dram cell

Details Method of making porous-si capacitor dram cell Method of making porous-si capacitor dram cell

1996-11-18

1998-09-29

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438255, H01L 2120

Patent

active

058145494

ABSTRACT:
A method of manufacturing porous-Si capacitors for use in semiconductor memories is disclosed herein. The present invention includes a SOG layer as an etching mask to etch a polysilicon layer to form a porous-Si structure. The etching process is performed to etch a portion of the first conductive layer and to etch away the remaining HSG-Si. Next, the residure SOG layer is removed to define a porous-Si bottom storage. Utilizing the porous-Si structure, the present invention can be used to increase the surface area of the capacitor.

REFERENCES:
patent: 5254503 (1993-10-01), Kenney
patent: 5256587 (1993-10-01), Jun et al.
patent: 5342800 (1994-08-01), Jun

Affiliated with

Also associated with

Rating

Method of making porous-si capacitor dram cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making porous-si capacitor dram cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making porous-si capacitor dram cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-685893