Static information storage and retrieval – Read only systems – Semiconductive
Patent
1994-07-25
1997-02-04
Zarabian, A.
Static information storage and retrieval
Read only systems
Semiconductive
365 63, G11C 1700
Patent
active
056005865
ABSTRACT:
A flat-cell ROM array includes a bank of field effect transistors, each having a source, drain and gate, formed by ion implantation between columns of buried N+ and under rows of polysilicon, wherein adjacent columns of buried N+ are the source and drain of at least one transistor and a corresponding row of polysilicon is the gate of the transistor. Each of these transistors is programmed to have one of a plurality of threshold voltages depending on a desired storage value. Attached to the bank of transistors is an upper selector network associated with the bank connected to a first class of alternating sets of the columns, and a lower selector network associated with the bank connected to a second class of alternating sets of the columns. A method provides steps for performing the present invention.
REFERENCES:
patent: 5111428 (1992-05-01), Liang et al.
patent: 5117389 (1992-05-01), Yiu
patent: 5280442 (1994-01-01), Hotta
patent: 5295092 (1994-03-01), Hotta
patent: 5386381 (1995-01-01), Takizawa
patent: 5418175 (1995-05-01), Hsue
patent: 5453392 (1995-09-01), Hong
"Semiconductor Memory Device and Process for Producing Same"; Sharp Kabushiki Kaisha; European patent application 88306931.2; Filed Jul. 27, 1988; Publication #0 302 659, Feb. 2, 1989.
"16Mb ROM Design Using Bank Select Architecture"; Mikiro Okada et al.; Sharp Corporation; 1988 VLSI Circuits Symposium (Tokyo), Digest of Technical Papers; Aug. 22-24, 1988; pp. 85-86.
Aplus Integrated Circuits, Inc.
Zarabian A.
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