Hardware simulation and design verification system and method

Details Hardware simulation and design verification system and method Hardware simulation and design verification system and method

1994-07-08

1997-02-04

Teska, Kevin J.

Boots, shoes, and leggings

364149, 364150, 395500, G06F 9455, G06F 1314

Patent

active

056005792

ABSTRACT:
A hardware design verification system has a hardware simulator, a test script, and a dispatcher, each preferably running as concurrent processes on a computer. The test script language is independent of the hardware simulator language. The hardware simulator simulates a hardware environment having a circuit under test coupled to a master model. To manipulate the hardware environment, the test script transmits a first packet to the dispatcher, the first packet being encoded in accordance with a predetermined encryption technique and designating a desired manipulation of the simulated hardware environment. The dispatcher, in response to receipt of the first packet, transmits the first packet to the master model, which in response decodes the first packet in accordance with the predetermined encryption technique and manipulates the hardware environment in accordance with the desired manipulation. In a preferred embodiment, the hardware simulator, dispatcher, and test script each rely on operating system facilities for packet transmission. For example, where the operating system is the UNIX system, one UNIX socket is dedicated for packet transmission between the test script and the dispatcher, and a second UNIX socket is dedicated to packet transmission between the hardware simulator and the dispatcher. When a desired hardware environment manipulation includes detecting the value of a signal in the circuit under test, the master model uses the predetermined encryption technique to encode the detected value into a packet. The packet is transmitted to the dispatcher, which forwards the packet to the test script.

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