Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-12-30
2000-02-29
Fahmy, Wael
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438437, 438525, H01L 2176
Patent
active
060308826
ABSTRACT:
A method for manufacturing shallow trench isolation structure in a substrate, in which by forming a doped region at the upper corners of a trench, the degree of oxidation in that region increases when the liner layer is formed over the exposed surface of the trench. Therefore, thickness of the liner layer at the upper corner regions of the trench is almost the same as in other regions. Consequently, a kink effect is prevented when a gate is subsequently formed over the active region of the substrate.
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patent: 5436189 (1995-07-01), Reasom
patent: 5780353 (1998-07-01), Omid-Zohoor
patent: 5841170 (1998-11-01), Adan et al.
Fahmy Wael
Huang Jiawei
Pham Long
United Semiconductor Corp.
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