Boots – shoes – and leggings
Patent
1985-11-04
1989-04-11
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 928
Patent
active
048211877
ABSTRACT:
A processor comprises first and second operation units, a first program memory which contains first microinstructions for controlling the first operation unit and second microinstructions for controlling at least the second operation units, a second program memory which contains microinstructions for controlling the second operation unit, first control means connected to the first program memory for controlling the first operation unit and the second operation unit, and second control means connected to the second program memory for controlling the second operation unit. In a normal mode, all operation units are under control of the first control means and in a multiprogram mode, the first operation unit is under control of the first control means and the second operation unit is under control of the second control means. These two mode operations are selected in accordance with the microinstructions stored in the first or second program memories.
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patent: 4156279 (1979-05-01), Wilhite
patent: 4251862 (1981-02-01), Murayama
patent: 4430707 (1984-02-01), Kim
patent: 4507728 (1985-03-01), Sakamoto et al.
Hagiwara Yoshimune
Kaneko Kenji
Matsushima Hitoshi
Ueda Hirotada
Chun Debra A.
Hitachi , Ltd.
Shaw Gareth D.
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