Memory address decoding system

Details Memory address decoding system Memory address decoding system

1985-09-16

1989-04-11

Chan, Eddie P.

Boots, shoes, and leggings

G06F 1300, G06F 700

Patent

active

048211826

ABSTRACT:
The computer system of this invention has a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data. Features of the present invention include a special reset scheme for the CPU, a multiplexing scheme for addressing the RAM, a technique for simply altering the control to provide capabilities of different capacity memories, alternate display of characters to provide either a 32-character line or a 64-character line, an improved keyboard selection scheme, and improved video processing means.

REFERENCES:
patent: 3969701 (1976-07-01), Hemdal
patent: 4028683 (1977-06-01), Divine et al.
patent: 4040029 (1977-08-01), Young
patent: 4328558 (1982-05-01), Musa et al.

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