Signal processing apparatus capable of processing received signa

Multiplex communications – Communication techniques for information carried in plural... – Byte assembly and formatting

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370509, 370543, 341100, 714800, 375354, H04J 306, H04J 322

Patent

active

060977353

ABSTRACT:
In a signal processing circuit capable of handling different signal rates, an STS-3 signal input as 78 M.times.2 parallel signals is converted by a serial-to-parallel converter into 19 M.times.8 parallel signals, thus making the number of signal lines equal to that of an STS-12 signal input as 78 M.times.8 parallel signals. Depending on whether the mode is STS-12 mode or STS-3 mode, a first selector selects the 78 M.times.8 parallel signals of STS-12 or the 19 M.times.8 parallel signals of STS-3, and supplies the selected signals to a signal processor. Depending on whether the mode is STS-12 mode or STS-3 mode, a second selector selects a 78-M clock or a 19-M clock and supplies the selected clock to the signal processor.

REFERENCES:
patent: 5715248 (1998-02-01), Lagle, III et al.
patent: 5729227 (1998-03-01), Park
patent: 5808571 (1998-09-01), Kuwata et al.
patent: 5946327 (1999-08-01), Murphy
patent: 6018305 (2000-01-01), Kikuchi et al.

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