System of selective purging of address translation in computer m

Details System of selective purging of address translation in computer m System of selective purging of address translation in computer m

1988-08-15

1989-04-11

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1210

Patent

active

048211710

ABSTRACT:
When data is subject to relocation in the physical memory of a processing system employing a virtual memory architecture, execution of programs can be greatly improved through the use of a validation code generator, which assigns a code to each virtual-to-physical address translation prior to its entry in the address translation system. Whenever a page in memory is replaced or the buffer is purged for memory management purposes, the code generator proceeds to another code and assigns this new code to subsequent entries.

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