Nonvolatile semiconductor memory device whose addresses are sele

Details Nonvolatile semiconductor memory device whose addresses are sele Nonvolatile semiconductor memory device whose addresses are sele

1998-11-06

2000-08-01

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518511, 36518529, G11C 800

Patent

active

060976667

ABSTRACT:
A block size buffer and block address pre-decoder are provided for a flash memory. At the time of data erase, the size of a block to be erased is input to the block size buffer and a set of block addresses is input to the block address pre-decoder. An output signal of the block size buffer is supplied to and decoded by the block address pre-decoder, a row decoder is controlled based on the result of pre-decoding, and a plurality of addressing including the above block address as a top address are selected in a multiple manner. Then, a plurality of successive blocks are simultaneously selected to simultaneously erase data in the memory cells in the plurality of blocks.

REFERENCES:
patent: 5239505 (1993-08-01), Fazio et al.
patent: 5355342 (1994-10-01), Ueoka
patent: 5367495 (1994-11-01), Ishikawa
patent: 5418752 (1995-05-01), Harari et al.
Kang-Deog Suh et al.; IEEE Journal of Solid-State Circuits, vol. 30; "A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme"; Nov. 1995; pp. 1149-1156.
Yoshihisa Iwata et al.; IEEE Journal of Solid-State Circuits, vol. 30; "A 35 ns Cycle Time 3.3 V Only 32 Mb NAND Flash EEPROM"; Nov. 1995; pp. 1157-1164.

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