Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-04-02

2000-08-01

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365 51, 365 63, G11C 800

Patent

active

060976608

ABSTRACT:
A semiconductor memory device comprises a plurality of memory banks each having a plurality of memory cell arrays and a plurality of sense amplifiers such that the memory cell arrays and the sense amplifiers are alternately disposed in a first direction, the memory banks being disposed in a second direction perpendicular to the first direction, a plurality of row decoders respectively provided in the first direction for the plurality of memory banks, a column decoder provided in the second direction with respect to the plurality of memory banks, a plurality of first data lines respectively provided in the second direction for the plurality of memory banks, and connected with the plurality of sense amplifiers in accordance with a signal outputted from the column decoder, a plurality of second data lines provided in the second direction, penetrating through the plurality of memory banks, and shared by the plurality of first data lines disposed for the plurality of memory banks, and a plurality of switching elements each having a first end connected to one of the plurality of first data lines and a second end connected to one of the plurality of second data lines, and controlled by a bank activation signal of a memory bank corresponding to the first data line connected to the first ends.

REFERENCES:
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patent: 5563820 (1996-10-01), Wada et al.
patent: 5621690 (1997-04-01), Jungroth et al.
patent: 5644527 (1997-07-01), Kubota
patent: 5648928 (1997-07-01), Yoon et al.
patent: 5894448 (1999-04-01), Amano et al.
Jei-Hwan Yoo, Chang-Hyun Kim ; IEEE J.S.S.C. vol. 31, No. 11; A 32-Bank 1 GB Self-Strobing Synchronous Drams with 1 GBYTE/S Bandwidth; Nov. 1996; pp. 1635-1644.

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