Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-02-11

2000-08-01

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

36518521, G11C 1606

Patent

active

060976381

ABSTRACT:
An EEPROM employs, as a scheme of detecting data of a memory cell in a memory cell array, a scheme of detecting the potential of a bit line potential sense node, which depends on the relationship in amplitude between the current for charging a bit line from a current source and the discharge current flowing to a selected cell using a sense amplifier. The sense amplifier is arranged in correspondence with one bit line and includes a constant current source transistor for charging the corresponding bit line, a latch circuit for latching memory cell data read out to the bit line potential sense node, and a switch transistor for turning on/off the charge path to the bit line based on data of the latch circuit. In the verify read mode, the cell current between the Vcc node and Vss node of a cell not to be written or a completely written cell can be turned off, so verification can be performed without flowing any unnecessary current.

REFERENCES:
patent: 5357462 (1994-10-01), Tanaka et al.

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