Multi-value dynamic semiconductor memory device having twisted b

Details Multi-value dynamic semiconductor memory device having twisted b Multi-value dynamic semiconductor memory device having twisted b

1998-11-18

2000-08-01

Tran, Andrew Q.

Static information storage and retrieval

Interconnection arrangements

365 51, 365190, 365206, 365168, G11C 506

Patent

active

060976209

ABSTRACT:
In a region of a transfer gate provided in a central portion of multilevel writing bit lines, noise in adjacent bit lines at the time of re-writing is counteracted by reversing the order of complementary bit line pair every other pair. With this, in a multilevel dynamic type semiconductor memory device in which one sense amplifier commonly includes a plurality of bit lines and some of the bit lines are selectively activated in a time-dividing manner, the influence of noise between the adjacent bit lines can be deleted.

REFERENCES:
patent: 5475643 (1995-12-01), Ohta
patent: 5625585 (1997-04-01), Ahn et al.
patent: 5629887 (1997-05-01), Nakano et al.
patent: 5949698 (1999-09-01), Shirley

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