Fishing – trapping – and vermin destroying
Patent
1993-06-07
1995-04-18
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
435242, 435 42, 435 43, 257411, H01L 21285
Patent
active
054078709
ABSTRACT:
A process for fabricating a high-reliability composite dielectric layer (19) includes the formation of a first oxynitride layer (14) on the surface (12) of a silicon substrate (10). The formation of the first oxynitride layer (14) is followed by an oxidation step to form a silicon dioxide layer (16) at the surface (12) of the substrate (10) and underlying the first oxynitride layer (14). The composite dielectric layer (19) is completed by exposing the substrate (10) to nitrous oxide, and diffusing a nitrogen bearing species through both the silicon dioxide layer (16) and the first oxynitride layer (14) to form a second oxynitride layer (18) underlying the silicon dioxide layer (16). The composite dielectric layer (19) exhibits a nitrogen-rich region at the interface between second oxynitride layer (18) and the silicon substrate (10). A second nitrogen rich region is also formed near the surface of the first oxynitride layer (14).
REFERENCES:
patent: 5198392 (1993-03-01), Fukuda et al.
patent: 5225361 (1993-07-01), Kakiuchi et al.
patent: 5254506 (1993-10-01), Hori
patent: 5258333 (1993-11-01), Shappir et al.
patent: 5278087 (1994-01-01), Jenq
Yoon, et al., "MOS Characteristics of NH3-Nitrided N20-Grown Oxides," IEEE Electron Dev. Letters, (14), No. 4, pp. 179-181 (Apr. 1993).
Ohnishi, et al., "Ultrathin Oxide/Nitride/Oxide/Nitride Multilayer Films for Mbit DRAM Capacitors," Solid State Devices & Materials Ext. Abstracts of '92 Int. Conf., pp. 67-69 (1992).
Haddad, et al., "Improvement of Thin-Gate Oxide Integrity Using Through-Silicon-Gate Nitrogen Ion Implantation," IEEE Electron Dev. Letters, vol. EDL-8 No. 2, pp. 58-60 (1987).
Ahn, et al., "Furnace Nitridation of Thermal SiO2 in Pure N2O Ambient for ULSI MOS Applications," IEEE Electron Device Letters, vol. 13, No. 2, pp. 117-119 (Feb. 1992).
Lo, et al., "Improved Hot-Carrier Immunity in CMOS Analog Device with N2O-Nitrided Gate Oxides" IEEE Electron Dev. Letters, vol. 13, NO. 11, pp. 457-459 (Sep. 8, 1992).
Fukuda, et al., "High-Performance Scaled Flash-Type EEPROMs with Heavily Oxynitrided Tunnel Oxide Films," IEDM, pp. 465-468 (1992).
Lo, et al., "Improved Performance and Reliability of MOSFETs with Ultrathin Gate Oxides . . . ," Symposium on VLSI Technology, pp. 43-44 (1991).
Anonymous (R1788), "Under-grown multiple dielectric-layer semiconductor device," Research Disclosure 18756, Derwent Publications, Nov., 1979.
Okada Yoshio
Tobin Philip J.
Chaudhuri Olik
Dockrey Jasper W.
Motorola Inc.
Mulpuri S.
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