High-speed, high-drive output buffer circuits with reduced groun

Details High-speed, high-drive output buffer circuits with reduced groun High-speed, high-drive output buffer circuits with reduced groun

1988-01-27

1989-04-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307473, 307475, 307270, 307279, H03K 301, H03K 2110

Patent

active

048209422

ABSTRACT:
A high-speed, high-drive output buffer circuit for providing an output signal at an output node with reduced ground bounce includes an AC buffer (12) and a DC buffer (14). The AC buffer (12) is formed of a first pull-up transistors (Q1) and a first pull-down transistor (Q2) connected in series and is responsive to a data input signal for generating quickly high-to-low and low-to-high transitions at the output node. The DC (14) buffer is formed of a second pull-up transistor (Q3) and a second pull-down transistor (Q4) connected in series and is responsive to the data input signal for generating slowly high-to-low and low-to-high transitions at the output node. The second pull-up transistor (Q3) is delayed in its turn-on with respect to the turn-on of the first pull-up transistor (Q1) when the output node is making the low-to-high transition so as to reduce the ground bounce. Similarly, the second pull-down transistor (Q4) is delayed in its turn-on with respect to the turn-on of said first pull-down transistor (Q2) when the output node is making the high-to-low transition so as to reduce the ground bounce.

REFERENCES:
patent: 4251740 (1981-02-01), Wilwerding
patent: 4508981 (1985-04-01), Dorler et al.
patent: 4527077 (1985-07-01), Higuchi et al.
patent: 4613771 (1986-09-01), Gal

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