Past-history filtered branch prediction

Details Past-history filtered branch prediction Past-history filtered branch prediction

1994-12-08

1996-10-08

Eng, David Y.

Boots, shoes, and leggings

3642617, 3649382, G06F 940

Patent

active

055641180

ABSTRACT:
A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

REFERENCES:
patent: 4370711 (1983-01-01), Smith
Two-Level Adaptive Training Branch Prediction Yeh et al. International Symposium on Microarchitecture After Nov. 18-20, 1991 Paper # 0-89791-460-0/91/0011/0051.
Instruction Reordering for Fork-Join Parallelism, After Jun. 20-22, 1990 Paper # 0-89791-364-7/90/006/0322.
Alternative Implementations of Two-Level Adaptive Branch Prediction, Yeh, et al. The 19th Annual Symposium on Computer Architecture May 1992.
US Patent Application Ser. No. 07/546,364 I-Cache Next Line Prediction.
US Patent Application Ser. No. 07/546,411 One Cycle Register Mapping.
Dynamic Instruction Scheduling and the Astronautics ZS-1, James E. Smith, Jul. 1989, Computer Magazine.

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