Semiconductor memory device having hierarchical bit line arrange

Details Semiconductor memory device having hierarchical bit line arrange Semiconductor memory device having hierarchical bit line arrange

1996-03-13

1998-02-03

Clawson, Jr., Joseph E.

Static information storage and retrieval

Interconnection arrangements

Transistors or diodes

365 51, 365 63, 365208, 365203, 365190, 365205, 365210, G11C 510

Patent

active

057151890

ABSTRACT:
The DRAM includes a plurality of main bit line pairs, a plurality of sense amplifiers, a plurality of word lines, a plurality of sub bit lines, a plurality of transfer gates, and a plurality of memory cells. The plurality of sub bit line pairs are arranged along each main bit line pair. The parasitic capacitance per unit length of a main bit line pair is at most 1/4 that of a sub bit line pair. Each transfer gate connects one main bit line and one sub bit line in response to a prescribed control signal. Thus, sufficiently large potential difference is generated between the main bit lines, and therefore the sense amplifier can surely amplify the potential difference.

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A 34-NS 16-MB Dram With Controllable Voltage Down-Converter, Hideto Hidaka et al., Jul. 102, IEEE Journal of Solid-State Circuits, vol. 27. pp. 1020-1027.
3-Dimensional Stacked Capacitor Cell For 16M and 64M Drams, T. Ema et al., IEDM Technical Digest Dec., 1988, p. 592.
Fam 19.3: A 1MB CMOS DRAM With Design-For-Test Functions, Joseph Neal et al., ISSCC 86, IEEE International Solid-State Circuits Conference, p. 264 (ISSCC).
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