Signal processing integrated circuit for row and column addition

Details Signal processing integrated circuit for row and column addition Signal processing integrated circuit for row and column addition

1987-12-21

1989-10-03

Harkcom, Gary V.

Boots, shoes, and leggings

364758, G06F 752

Patent

active

048721344

ABSTRACT:
A signal-processing circuit performs a cosine type transformation (double addition in rows and columns) of values of a matrix of n rows and n columns. An architecture is proposed with a row transform circuit, a column transform circuit and a buffer memory of nxn words. The memory is addressed sequentially, line by line, during the storage of nxn coefficients C.sup.i (v) which are the results of the row transform on a block of nxn data. Then it is addressed sequentially, column by column, during the storage of nxn coefficients C.sup.i (v) corresponding to the processing of the following block. At each address, a read stage of a coefficient is performed followed by the writing of a new coefficient. The invention can be applied to circuits for the digital processing of images to prepare the compression of data before transmission.

REFERENCES:
patent: 4044243 (1977-08-01), Cooper et al.
patent: 4573136 (1986-02-01), Rossiter

Affiliated with

Also associated with

Rating

Signal processing integrated circuit for row and column addition does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Signal processing integrated circuit for row and column addition, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal processing integrated circuit for row and column addition will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-668469