Enhanced CPU return address stack

Details Enhanced CPU return address stack Enhanced CPU return address stack

1987-11-02

1989-10-03

Eng, David Y.

Boots, shoes, and leggings

G06F 938, G06F 940, G06F 942

Patent

active

048721093

ABSTRACT:
Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and return to a desired line after a delayed call.

REFERENCES:
patent: 3401376 (1968-09-01), Barnes et al.
patent: 3789365 (1974-01-01), Jen et al.
patent: 3924245 (1975-12-01), Eaton et al.
patent: 4394729 (1983-07-01), Armstrong
patent: 4553203 (1985-11-01), Rau et al.

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