Method of making a multi-layer circuit assembly

Details Method of making a multi-layer circuit assembly Method of making a multi-layer circuit assembly

1991-12-31

1994-11-29

Arbes, Carl J.

Metal working

Method of mechanical manufacture

Electrical device making

29852, 156902, 174260, 174262, 439 69, H05K 336

Patent

active

053677641

ABSTRACT:
A multi-layer circuit panel assembly is formed by laminating circuit panels with interposers incorporating flowable conductive material at interconnect locations and a flowable dielectric materials at locations other than the interconnect locations. Excess materials are captured in reservoirs such as within vias in the circuit panels and apertures in interior elements within the interposers. The flowable materials of the interposers, together with the reservoirs, allow the interposers to compress and take up tolerances in the components. The flowable dielectric material encapsulates conductors on the surfaces of the circuit panels.

REFERENCES:
patent: 3077511 (1963-02-01), Bohrer et al.
patent: 3214827 (1965-11-01), Phohofsky
patent: 3316618 (1967-05-01), Guarracini
patent: 3316619 (1967-05-01), Beelitz
patent: 3509270 (1970-04-01), Dube et al.
patent: 3541222 (1970-11-01), Parks et al.
patent: 3546775 (1970-12-01), Lalmond et al.
patent: 3561110 (1971-02-01), Feulner et al.
patent: 3606677 (1971-09-01), Ryan
patent: 3616532 (1971-11-01), Beck
patent: 3739469 (1973-06-01), Dougherty, Jr.
patent: 3775844 (1973-12-01), Parks
patent: 3795037 (1974-03-01), Luttmer
patent: 3795047 (1974-03-01), Abolafia et al.
patent: 3829601 (1974-08-01), Jeannotte et al.
patent: 3859711 (1975-01-01), McKiddy
patent: 3862790 (1975-01-01), Davies et al.
patent: 4024629 (1977-05-01), Lemoine et al.
patent: 4211603 (1980-07-01), Reed
patent: 4216350 (1980-08-01), Reid
patent: 4249032 (1981-02-01), Crepeau
patent: 4249302 (1981-02-01), Crepeau
patent: 4383363 (1983-05-01), Hayakawa et al.
patent: 4394712 (1983-07-01), Anthony
patent: 4452847 (1984-06-01), Siemon
patent: 4479991 (1984-10-01), Thompson
patent: 4511757 (1985-04-01), Ors et al.
patent: 4642889 (1987-02-01), Grabbe
patent: 4712161 (1987-12-01), Pryor et al.
patent: 4729809 (1988-03-01), Dery et al.
patent: 4740411 (1988-04-01), Shaheen
patent: 4755911 (1988-07-01), Suzuki
patent: 4788766 (1988-12-01), Burger et al.
patent: 4793814 (1988-12-01), Zifcak et al.
patent: 4935584 (1990-06-01), Boggs
patent: 4954878 (1990-03-01), Fox et al.
patent: 4970106 (1990-11-01), DiStefano et al.
patent: 5089880 (1992-02-01), Meyer et al.
patent: 5121299 (1992-06-01), Frankeny et al.
patent: 5128831 (1992-07-01), Fox, III et al.
patent: 5129142 (1992-07-01), Bindra et al.
patent: 5140745 (1992-08-01), McKenzie, Jr.
patent: 5224265 (1993-07-01), Dux et al.
patent: 5232598 (1993-08-01), Ehrenber et al.
IBM Technical Disclosure Bulletin, vol. 21, No. 4, Sep. 1978 "Multilayer Laminated Chip Carrier", pp. 1396-1397.

Affiliated with

Also associated with

Rating

Method of making a multi-layer circuit assembly does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making a multi-layer circuit assembly, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a multi-layer circuit assembly will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-66773