Method of manufacturing LDDFET having double sidewall spacers

Details Method of manufacturing LDDFET having double sidewall spacers Method of manufacturing LDDFET having double sidewall spacers

1991-07-19

1993-02-02

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437238, 437200, 257344, 257384, 257900, H01L 21336

Patent

active

051837714

ABSTRACT:
In an MIS transistor of a type having LDD and salicide structures, the location of the boundary between the high and low impurity density source/drain regions and the positions of the salicide layers on the source/drain regions are independently controlled during fabrication using a double gate sidewall structure. An MIS transistor improved thereby has its boundary between the high and low impurity density source/drain regions at or displaced toward the control gate electrode with respect to the interface of the double gate sidewall structure.

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Author Unknown, "Simplified Lightly Doped Drain Process" IBM Technical Disclosure Bulletin, vol. 30, No. 12, May 1988, pp. 180-181.
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Ghandhi, VLSI Fabrication Principles, John Wiley and Sons, 1983, pp. 435-439.
Ryuichi Izawa et al. "The Impact of Gate-Drain Overlapped LDD (Gold) for Deep Submicron VLSI's", IEDM 87 (1987) pp. 38-41.

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