Boots – shoes – and leggings
Patent
1994-09-30
1996-10-08
Beausoliel, Jr., Robert W.
Boots, shoes, and leggings
395375, 3642624, 364DIG1, G06F 1134
Patent
active
055641113
ABSTRACT:
A non-blocking translation lookaside buffer is described for use in a microprocessor capable of processing speculative and out-of-order instructions. Upon the detection of a fault, either during a translation lookaside buffer hit or a page table walk performed in response to a translation lookaside buffer miss, information associated with the faulting instruction is stored within a fault register within the translation lookaside buffer. The stored information includes the linear address of the instruction and information identifying the age of instruction. In addition to storing the information within the fault register, a portion of the information is transmitted to a reordering buffer of the microprocessor for storage therein pending retirement of the faulting instruction. Prior to retirement of the faulting instruction, the translation lookaside buffer continues to process further instructions. Upon retirement of each instruction, the reordering buffer determines whether a fault had been detected for that instruction and, if so, the microprocessor is flushed. Then, a branch is taken into microcode. The microcode accesses the linear address and other information stored within the fault register of the translation lookaside buffer and handles the fault. The system is flushed and the microcode is executed only for faulting instructions which actually retire. As such, faults detected while processing speculative instructions based upon mispredicted branches do not prevent further address translations and do not cause the system to be flushed. Method and apparatus implementations are described herein.
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Akkary Haitham
Colwell Robert P.
Fetterman Michael A.
Glew Andrew F.
Hinton Glenn J.
Beausoliel, Jr. Robert W.
De'cady Albert
Intel Corporation
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