Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1996-11-14
1998-02-03
Whitehead, Jr., Carl W.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257734, 257736, 257750, 257764, 257774, H01L 2348, H01L 2352, H01L 2940
Patent
active
057148040
ABSTRACT:
An electrical connection structure is provided for protecting a barrier metal layer within a contact opening during the formation of an aluminum interconnection layer overlying a tungsten plugged connection structure. The deposited tungsten plug overlying the barrier metal layer is etched back sufficiently to create a slight recess at the opening. A thin layer of tungsten is then selectively deposited for filling the recess. This layer acts as an etch stop during aluminum interconnection layer formation and protects the underlying barrier metal layer.
REFERENCES:
patent: 4592802 (1986-06-01), Deleonibus et al.
patent: 4824521 (1989-04-01), Kulkarni et al.
patent: 5070391 (1991-12-01), Liou et al.
patent: 5374849 (1994-12-01), Tada
Wolf, Stanley, Silicon Processing for The VLSI Era, Lattice Press, Sunset Beach, California, 1990, vol. 2, "Process Integration," pp. 245-252.
Kaanta, Carter et al., Submicron Wiring Technology with Tungsten and Planarization, IBM General Technology Division, Essex Junction, Vermont 05452, pp. IEDM 87-209-IEDM 87-212, 1987.
Kaanta, Carter et al., Submicron Wiring Technology with Tungsten and Planarization, 1988 Proceedings Fifth International IEEE VLSI Multilevel Interconnection Conference, Jun. 13-14, 1988, Santa Clara, CA., pp. 21-28.
Lee, Pei-Ing, John Cronin and Carter Kaanta, "Chemical Vapor Deposition of Tungsten (CVD W) as Submicron Interconnection and Via Stud," J. Electrochem. Soc. 136:(7), pp. 2108-2112, 1989.
Estabil, J.J., H.S. Rathore and E.N. Levine, Electromigration Improvements with Titanium Underlay and Overlay in AL(Cu) Metallurgy, Jun. 11-12, 1991 VMIC Conference, General Technology Division, IBM Corporation, Hopewell Junction, NY 12533, pp. 242-yy248.
Miller Robert O.
Smith Gregory C.
Carlson David V.
Galanthay Theodore E.
Jorgenson Lisa K.
SGS-Thomson Microelectronics Inc.
Whitehead Jr. Carl W.
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