Process design for wafer edge in vlsi

Details Process design for wafer edge in vlsi Process design for wafer edge in vlsi

1998-02-13

1999-10-12

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

438598, 438599, H01L 2120

Patent

active

059666285

ABSTRACT:
A wafer structure and method of forming a wafer structure with all of the dielectric material and conducting material films removed from the outer periphery of the wafer in order to protect the dielectric and conducting films from damage due to wafer handling, storage, or clamping. The dielectric or conducting material is removed from the wafer edge using wafer edge exposure or edge bead rinse methods. The wafer edge exposure method is carried out at the same time the dielectric or conducting layer is being patterned.

REFERENCES:
patent: 4510176 (1985-04-01), Cuthbert et al.
patent: 5168201 (1992-12-01), Arai et al.
patent: 5366906 (1994-11-01), Wojnarowski et al.
patent: 5370766 (1994-12-01), Desaigoudar et al.
patent: 5425846 (1995-06-01), Koze et al.
patent: 5556506 (1996-09-01), Contreras et al.
patent: 5578532 (1996-11-01), Van De Ven et al.
patent: 5580829 (1996-12-01), Browning et al.
patent: 5714396 (1998-02-01), Robb et al.

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