Method of making a multiple mushroom shape capacitor for high de

Details Method of making a multiple mushroom shape capacitor for high de Method of making a multiple mushroom shape capacitor for high de

1997-12-22

1999-10-12

Trinh, Michael

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438254, 438255, H01L 2120

Patent

active

059666129

ABSTRACT:
A new structure of a capacitor for a DRAM is disclosed herein. The structure of the capacitor includes a mushroom shape first storage node, a dielectric layer and a second storage node. The mushroom shape first storage node includes a base portion that is formed of polysilicon. A plurality of mushroom neck portions located on the base portion. A plurality of roof portions are connected on the tops of the mushroom neck portions. The dielectric layer is conformally covered the surface of the mushroom shape storage node. The second storage node encloses the surface of the dielectric layer. The formation of the mushroom shape capacitor includes forming a first conductive layer over a wafer. Then, an undoped hemispherical grains silicon (HSG-silicon) is formed on the first conductive layer. The HSG-silicon is separated along the grain boundaries to expose a portion of the first conductive layer. Next, the exposed first conductive layer is etched by using the HSG-silicon layer as a mask. A dielectric layer is then deposited on the exposed surface of the first conductive layers, and the HSG-silicon. A second conductive layer is formed over the dielectric layer.

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Shye Lin Wu et al., Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon (TOPS), IEEE Electron Device Letters, vol. 14, No. 8, Aug. 1993, pp. 379-381.
Sanggi Yu et al., The Honeycomb-Shape Capacitor Structure for ULSI DRAM, IEEE Electron Device Letters, vol. 14, No. 8, Aug. 1993, pp. 369-371.
S.H. Woo et al., Selective Etching Technology of in-situ P Doped Poly-Si (SEDOP) for High Density DRAM Capacitors, 1994 Symposium on VLSI Technology Digest of Technical Papers, 1994, pp. 25-26.
M.Sakao et al., A Capacitor-Over-Bit-Line (COB) Cell With A Hemispherical-Grain Storage Node for 64Mb DRAMs, 1990 IEEE, 1990, pp. 27.3.1-27.3.4.

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