Method of making an ultra high density NAND gate using a stacked

Details Method of making an ultra high density NAND gate using a stacked Method of making an ultra high density NAND gate using a stacked

1996-11-07

1998-02-03

Dutton, Brian

Fishing, trapping, and vermin destroying

437 57, 437915, H01L 21265, H01L 2170, H01L 2700

Patent

active

057143943

ABSTRACT:
A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows development of a high density NAND gate. The NAND gate includes two pairs of stacked transistors, wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair.

REFERENCES:
patent: 4768076 (1988-08-01), Aoki et al.
patent: 4902637 (1990-02-01), Kondou et al.
patent: 5348899 (1994-09-01), Dennison et al.
patent: 5612552 (1997-03-01), Owens

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