Phase detector employing quadruple memory elements

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

328110, 307247R, H03K 520

Patent

active

040272621

ABSTRACT:
A phase detector which employs four memory elements suitably comprised by D-type flip-flops. The detector provides an output dependent upon the phase difference between two input signals. One pair of memory elements is clocked by one input signal. The other pair of memory elements is clocked by the other input signal. The memory elements are so arranged that when the ratio of the frequencies of the input signals is less than 2:1, the detector provides three output states which may be used in a phase locked oscillator to cause, in the first state, an increase in the frequency of one input signal; in the second state, no frequency change; and in the third state, a decrease in frequency. Above a frequency ratio of 2:1, the detector never enters the second state. Elimination of the second state under such conditions decreases the time required for a phase locked oscillator with this detector to achieve phase lock.

REFERENCES:
patent: 3354398 (1967-11-01), Broadhead
patent: 3458823 (1969-07-01), Nordahl
patent: 3714463 (1973-01-01), Laune
patent: 3735324 (1973-05-01), Phillips
patent: 3755746 (1973-08-01), Hogue et al.
patent: 3944933 (1976-03-01), Gallet

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