Data speculatable processor having reply architecture

Details Data speculatable processor having reply architecture Data speculatable processor having reply architecture

1996-11-13

1999-10-12

An, Meng-Ai T.

39580001, 39580023, 395376, 395385, 395386, 395393, G06F 1300

Patent

active

059665440

ABSTRACT:
A microprocessor having a replay architecture with an execution core for performing data speculation in executing an instruction, a delay unit for making a copy of the instruction and holding the copy for as long as the instruction takes to execute, and a checker for determining whether the data speculation was bogus. If the data speculation was bogus, the delay unit and its buffer send the copy of the instruction back to the execution core for re-execution. A multiplexor coupled to the input of the execution core selects for execution among original instructions from the instruction cache, replay instructions from the delay unit, and manufactured instructions from various other units such as the TLB or tag units, according to a priority scheme.

REFERENCES:
patent: 5142634 (1992-08-01), Fite et al.
patent: 5153848 (1992-10-01), Elkind et al.
patent: 5309561 (1994-05-01), Overhouse et al.
patent: 5421021 (1995-05-01), Saini

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