System and method for analyzing static timing

Details System and method for analyzing static timing System and method for analyzing static timing

1997-05-09

1999-10-12

Teska, Kevin J.

3955004, G06F 1750

Patent

active

059665211

ABSTRACT:
The present invention provide a system and a method for analyzing the static timing for LSIs which involves rather a small number of false paths contained in output results and also which reduces the processing time required. A static-timing analysis technique according to the present invention comprises a net-list input step S110 which inputs per-transistor basis connection information, to construct an internal data structure for analysis; an expected-value check step S120 which checks, against the above-mentioned internal data structure, each node on whether its expected values may be a high-impedance state; a signal-flow direction narrow-down step S130 which narrows down the directions in which the transistor signal may flow, based on the obtained expected values; a division step S140 which divides a sequential circuit into units consisting of only combinational sub-circuits; a path search step S150 which searches paths for each of thus divided units; and an output step S170 which outputs the obtained results.

REFERENCES:
patent: 5355321 (1994-10-01), Grodstein et al.
patent: 5648909 (1997-07-01), Biro et al.
patent: 5650938 (1997-07-01), Booteh Saz et al.
patent: 5675728 (1997-10-01), Kunda et al.

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