Block decoded wordline driver with positive and negative voltage

Details Block decoded wordline driver with positive and negative voltage Block decoded wordline driver with positive and negative voltage

1998-07-24

1999-10-12

Phan, Trong

Static information storage and retrieval

Floating gate

Particular biasing

36518527, 36518518, 36518529, 365218, G11C 1604, G11C 1606

Patent

active

059663316

ABSTRACT:
The negative supply voltage and isolation well bias used by the drivers during sector or chip level erase operations are decoded separately from each other and from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry using shared isolation well MOS transistors coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, a third supply voltage source for the shared isolation well and a set of wordline drivers. The wordline drivers are coupled to the first, second and third supply voltage sources, and selectively drive wordlines in the set of wordlines with a wordline voltage from either the first supply voltage source or the second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors. Each supply voltage selector in the set is coupled with a subset of the set of drivers. The subset of drivers is coupled with a respective segment in the array. The supply voltage selectors select a negative erase supply voltage or an erase inhibit supply voltage during an erase mode in response to address signals identifying the respective segments. The selected negative erase supply voltage or erase inhibit supply voltage is applied to the subsets of the set of drivers which are coupled to the respective segment on a segment by segment basis.

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Umezawa, A. et al., "A 5-V-Only Operation 0.6-.mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1540-1546.
Venkatesh, B. et al., "A 55ns 0.35 .mu.m 5V-Only 16M Flash Memory with Deep-Power-Down", 1996, IEEE International Solid-State Circuits Conference, Paper No. JP 2.7, pp. 44-45.

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