Microprocessor architecture which facilitates input/output utili

Details Microprocessor architecture which facilitates input/output utili Microprocessor architecture which facilitates input/output utili

1994-12-08

1996-10-08

Bowler, Alyssa H.

395427, 395375, 395821, G06F 1300

Patent

active

055640575

ABSTRACT:
In processors with a reduced set of instructions the operands are derived from registers or as by a directly indicated number from a section of the instruction word, the operation result being stored in a register so that processing can take place within one clock cycle. However, when input/output data from peripheral apparatus is processed, a loss of time occurs because these values must first be transferred from the main memory to the corresponding registers. Acceleration is possible by providing additional registers which exchange input/output data directly with the corresponding peripheral apparatus and which can be connected directly to the ALU. In order to enable addressing of these additional input/output registers, additional bits are used as an address extension in the instruction word, said bits switching over between registers of the same address in the two sets of registers. These address extensions occur preferably at bit positions within the instruction word which are at least partly not evaluated, for example as is the case in instructions for SPARC processors when the second operand is indicated by a register. A compatible extension for faster processing of input/output data is thus possible. When a further bit position is used for the control bit, direct numbers in the instruction word can be indicated also in the case of extension.

REFERENCES:
patent: 4811202 (1989-03-01), Schabowski
patent: 4980819 (1990-12-01), Cushing et al.
patent: 5228130 (1993-07-01), Michael
patent: 5251307 (1993-10-01), Sugiyama
patent: 5404551 (1995-04-01), Katsuno
Janacek et al., "Register Array Processor", Microprocessing and Microprogramming, Aug. 1987, pp.23-30.
PD.mu.PD7720 from NEC.
Matoba et al., "Twin Register Architecture for AI Processor", IEEE, 1989, pp. 168-173

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