Memory system with bytewise data transfer control

Details Memory system with bytewise data transfer control Memory system with bytewise data transfer control

1974-06-25

1976-10-05

Wise, Edward J.

Communications: electrical

Digital comparator systems

G06F 300

Patent

active

039848116

ABSTRACT:
Memory system comprising a first memory and a second memory, in which memories a plurality of memory elements are arranged according to word locations and can be addressed by an address signal per word location, further comprising for each memory an instruction line for read and/or write instruction signals, driving devices and terminals in each memory which are interconnected by a data path line, and a control device capable of generating the instruction signals for addressing word location in the first memory for transferring information associated therewith as an information word via the data path line between the two memories.

REFERENCES:
patent: 3351909 (1967-11-01), Hummel
patent: 3417375 (1968-12-01), Packard
patent: 3566363 (1971-02-01), Driscoll, Jr.
patent: 3638194 (1972-01-01), Matsushita et al.
patent: 3670307 (1972-06-01), Arnold et al.
patent: 3705388 (1972-12-01), Nishimoto
patent: 3710349 (1973-01-01), Miwa et al.
patent: 3716838 (1973-02-01), Beard

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