Thin-film transistor and SRAM memory cell equipped therewith

Details Thin-film transistor and SRAM memory cell equipped therewith Thin-film transistor and SRAM memory cell equipped therewith

1997-11-24

1999-10-12

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

257 61, 257347, 257408, 257903, H01L 2904, H01L 2976

Patent

active

059659050

ABSTRACT:
A TFT with a drain-offset structure is provided, which realizes a high ON current while keeping an OFF current at a low level. This TFT includes a substrate and a patterned semiconductor film formed on a main surface of the substrate. At least the main surface of the substrate has an insulating property. The patterned semiconductor film is made of a silicon-system semiconductor material and is not monocrystalline. The patterned semiconductor film includes a source region of a first conductivity type, a channel region of a second conductivity type opposite to the first conductivity type, a first drain region of the first conductivity type, and a second drain region of the second conductivity type. The first drain region serves as an offset region. A gate electrode is formed to be opposite to the channel region through a gate insulating film. The source region is formed on one end of the semiconductor film. The second drain region is formed on an opposite end of the semiconductor film to the source region. The channel region is formed to be adjacent to the source region and the first drain region. The first drain region is formed to be adjacent to the channel region and the second drain region.

REFERENCES:
patent: 5489792 (1996-02-01), Hu et al.
patent: 5821585 (1998-10-01), Maegawa
F. Hayashi et al., "The Electrical Characteristics of Lightly-Doped-Offset Polysilicon TFT", Proceedings of 1991 Japan Applied Physics Society Spring Lecture-Meeting, Lecture No. 30p-T-2, p. 671.

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