Circuit arrangement for a time division multiplex communication

Details Circuit arrangement for a time division multiplex communication Circuit arrangement for a time division multiplex communication

1977-12-19

1979-01-16

Robinson, Thomas A.

325 4, H04J 306, H04J 312, H04M 716

Patent

active

041350600

ABSTRACT:
To combine specific information transmitted in the form of multiframes (i.e. signalling information in TDMA) channel by channel at the receiving end, this information is written into a RAM in parallel in order of receipt. The addresses of the RAM are divided into channel and frame addresses which are stepped on independently of each other for writing and reading. Writing and reading alternate in quick succession. When the end of a multiframe is detected in a channel, this channel address is retained during reading and the signalling information of this channel, starting with the beginning of the multiframe, is read out in parallel and translated into serial form. To do this, each channel has the same sufficient time available.

REFERENCES:
patent: 3772475 (1973-11-01), Loffreda
patent: 3843927 (1974-10-01), Hanni
patent: 3970799 (1976-07-01), Colton et al.

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