Memory access delay control circuit for image motion compensatio

Details Memory access delay control circuit for image motion compensatio Memory access delay control circuit for image motion compensatio

1994-12-29

1996-10-08

Lim, Krisna

395550, G06F 1300

Patent

active

055640397

ABSTRACT:
A memory access delay control circuit for image motion compensation in HDTV, which can adaptively delay read/write time of two frame memories and simply control the delay amount data. The circuit includes a section for providing delay amount data of a write address signal of the frame memories, a delay control section for providing delay control signal for delaying the write address signal as much as the value of the delay amount data, and an address counter section for counting and providing the write address signal in accordance with the delay control signal. According to the present invention, the delay amount data providing section may comprise a section for detecting actual delay amount of the write address signal by utilizing a frame synchronizing signal and a frame synchronizing write signal so as to automatically compensate for the inputted delay amount, thereby providing convenience in use.

REFERENCES:
patent: 4591909 (1986-05-01), Kuroda et al.
patent: 4958226 (1990-09-01), Haskell et al.
patent: 4985767 (1991-01-01), Haghiri et al.
patent: 5157742 (1992-10-01), Niihara

Affiliated with

Also associated with

Rating

Memory access delay control circuit for image motion compensatio does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory access delay control circuit for image motion compensatio, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory access delay control circuit for image motion compensatio will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-65170