Exclusive and/or partially inclusive extension cache system and

Details Exclusive and/or partially inclusive extension cache system and Exclusive and/or partially inclusive extension cache system and

1994-03-23

1996-10-08

Chan, Eddie P.

395449, 395460, G06F 1202

Patent

active

055640354

ABSTRACT:
A multi-level memory system is provided having a primary cache and a secondary cache in which unnecessary swapping operations are minimized. If a memory access request misses in the primary cache, but hits in the secondary cache, then the secondary cache responds to the request. If, however, the request also misses in the secondary cache, but is found in main memory, then main memory responds to the request. In responding to the request, the secondary cache or main memory returns the requested data to the primary cache. If an address tag of a primary cache victim line does not match an address tag in the secondary cache or the primary cache victim line is dirty, then the victim is stored in the secondary cache. The primary cache victim line includes a first bit for indicating whether the address tag of the primary cache victim line matches an address tag of the secondary cache.

REFERENCES:
patent: 5386547 (1995-01-01), Jouppi
"Some Thoughts On Memory System Research, " Norman P. Jouppi (NSF Memory System Work Shop at the University of Virginia, Apr. 12-13, 1993).

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