Boots – shoes – and leggings
Patent
1986-09-08
1990-01-23
Zache, Raulfe B.
Boots, shoes, and leggings
364243, 3642433, 364246, 3642461, 3642394, G06F 900
Patent
active
048962643
ABSTRACT:
A signal processing system (10) is described which has a processor (12), a random access memory (14) for storage of data, a read-only memory (16) for storage of both coefficients and instructions, and a selective cache memory (18) for storage of instructions that require high performance, and their associated buses. Instructions selected by the program are stored in the selective cache memory during their first call from the read only memory for use later in the program. An address sequencer (50) is described as one form of a control unit for executing the data stored in the selective cache memory. It generates a sequence of addresses repetitively, counts the number of iterations of the sequence of addresses, and informs the controller when a certain number of iterations have been completed. This creates a conditional branch statement in the program of the signal processing system (10).
REFERENCES:
patent: 4141067 (1979-02-01), McLagan
patent: 4181935 (1980-01-01), Feeser et al.
patent: 4195342 (1980-03-01), Joyce et al.
patent: 4197580 (1980-04-01), Chang et al.
patent: 4306287 (1981-12-01), Huang
Electronic Design, Feb. 20, 1986; Moving Memory Off Chip, DSP .mu.P Squeezes in More Computational Power; by John Roesgen and Sayuri Tung; pp. 131 to 140, Design Entry.
American Telephone and Telegraph Company
AT&T Bell Laboratories
Havill Richard B.
Mills John G.
Ulbrich Volker R.
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