Vertical DMOS power transistor with an integral operating condit

Details Vertical DMOS power transistor with an integral operating condit Vertical DMOS power transistor with an integral operating condit

1988-09-08

1990-01-23

Mintel, William

357 38, 357 28, 357 3214, H01L 2978

Patent

active

048961965

ABSTRACT:
A vertical DMOS or IGBT cell structure with an integral operating condition sensor provided by a sensor region forming a PN junction 65 with an adjacent region of the cell and having a sensor region contact 75 for conducting a test current without interfering with normal operation of the cell.

REFERENCES:
patent: 3614480 (1971-10-01), Berglund
patent: 3801949 (1974-04-01), Larrabee
patent: 4032953 (1977-06-01), Suzuki
patent: 4126496 (1978-11-01), Verderber
patent: 4242598 (1980-12-01), Johnson et al.
patent: 4260911 (1981-04-01), Brown et al.
patent: 4618872 (1986-10-01), Baliga
patent: 4635086 (1987-01-01), Miwa et al.
patent: 4698655 (1987-10-01), Schultz
patent: 4730228 (1988-03-01), Einzinger et al.
patent: 4760434 (1988-07-01), Tsuzuki et al.

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