System and method for mapping processor clock values in a multip

Details System and method for mapping processor clock values in a multip System and method for mapping processor clock values in a multip

1997-07-07

1999-10-12

Heckler, Thomas M.

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

Least weight routing

G06F 112

Patent

active

059648465

ABSTRACT:
The present invention is directed to a system and method for accurately and efficiently synchronizing and then mapping, or normalizing, processor clocks in a multiprocessor information handling system. The system and method of the present invention provide sufficient granularity for subcycle variations between processors, while taking into account the problem of clock drifts. A plurality of processors are selected for the purpose of synchronization. The clocks located on the processors are synchronized, and then time values between synchronization points are mapped from each secondary processor to an equivalent, or normalized, time value in a primary processor. To accomplish this mapping, three clock differences are calculated. The first clock difference is the time between the first and second synchronization points for the primary processor, and the second clock difference is the time between the first and second synchronization points for the secondary processor. The third clock difference is the time difference between the time value to be mapped in the secondary processor and the first synchronization point in the secondary processor. The third time difference is multiplied by the ratio of the first time difference to the second time difference, and then the result is added to the time value of the primary clock at the first synchronization point. The final result is the mapped, or normalized, time value.

REFERENCES:
patent: 3810119 (1974-05-01), Zieve et al.
patent: 4097860 (1978-06-01), Araseki et al.
patent: 4531185 (1985-07-01), Halpern et al.
patent: 4584643 (1986-04-01), Halpern et al.
patent: 4868514 (1989-09-01), Azevedo et al.
patent: 4899366 (1990-02-01), Davis et al.
patent: 4906944 (1990-03-01), Frerking
patent: 4959846 (1990-09-01), Apple et al.
patent: 5504878 (1996-04-01), Coscarella et al.
patent: 5613127 (1997-03-01), Schultz
IEEE, "A Distributed Real-Time Language and Its Operational Semantics," Proceedings of the Real Time Systems Symposium, Santa Monica, Dec. 5-7, 1989, No. Symp. 10, 5, Dec. 1989, pp. 41-50.
"Trace Synchronization in a Multiprocessor Environments," IBM Technical Disclosure Bulletin, vol. 35, No. 1B, Jun. 1992, pp. 161-162.
"Time-Stamp Synchronization for Parallel Trace Services," IBM Technical Disclosure Bulletin, vol. 36, No. 06B, Jun. 1993, pp. 283-284.

Affiliated with

Also associated with

Rating

System and method for mapping processor clock values in a multip does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for mapping processor clock values in a multip, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for mapping processor clock values in a multip will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-647834